EVONA

FPGA Design & Verification Engineer, Senior - Denver

Denver, CO

Job Description

FPGA Design & Verification Engineer, Senior

Posted: Tuesday, 10/17/2023
Lead FPGA Design & Verification Engineer
Denver, CO

Our exciting Space client is seeking a talented Lead FPGA Design & Verification Engineer to join the Electrical Systems team. The successful candidate will be a creative problem solver and life-long learner who continually seeks a deeper understanding and expertise of digital logic design. They must be attentive to detail and disciplined at documentation to ensure quality and maintainability in our products.

RESPONSIBILITIES:
  • Design, develop, and verify complex FPGA designs.
  • Register Transfer Level (RTL) coding in (System) Verilog and/or VHDL.
  • Debug and validate designs in a lab environment.
  • Generate design documentation.

QUALIFICATIONS
  • B.S. or M.S. in Electrical and/or Computer Engineering.
  • Knowledge and deep understanding of RTL coding using Hardware Description Languages (HDL).
  • Experience with SystemVerilog Object-Oriented Programming.
  • Design experience including design, debug, documentation, and review of RTL design blocks, including an understanding of reset and clocking architecture design.
  • Ability to debug and validate designs with use of lab tools such as oscilloscopes and logic analyzers.

DESIRED QUALIFICATIONS
  • Python, TCL, Make, and shell scripting.
  • Experience using ModelSim and/or QuestaSim.
  • Experience with UVM, Assertions, and Constrained Random Verification techniques.
  • Prior experience working with AMBA Protocols such as AXI or APB.
  • Develop and maintain an automated regression test environment.
  • Ability to analyze signal timing characteristics and formulate design constraints.
  • Knowledge of design techniques for radiation upset mitigation.
  • Experience developing signal processing algorithms such as filters, (de)modulators, linear recursive sequence generators, correlators, phase-locked loops, error detection and correction encoders/decoders, timing & synchronization, framing/de-framing, packetization, etc.

EVONA At A Glance

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